Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1

[paul <paulw@mmail.ath.cx>]

Hi

I'm new here. I see most of the projects are done in Verilog. Why Verilog?
Most school teach VHDL.... My university teach VHDL.
I really don't want to juggle two languages.

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