Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1

[Rudolf Usselmann <rudi@asics.ws>]

On Tue, 2003-05-20 at 17:42, paul wrote:
> Hi
> 
> I'm new here. I see most of the projects are done in Verilog. Why Verilog?
> Most school teach VHDL.... My university teach VHDL.
> I really don't want to juggle two languages.

You should ask your school (and the other schools you are
referring too), most of the industry is using Verilog.
Search the archives, I have posted a message a while back
in which the Synopsys CEO makes a statement that VHDL is
dead. Which is probably not quite true, but shows you that
the industry is at least trying to steer in to one direction ...

Regards, 
rudi               
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