Re: [openrisc] Cache invalidation & synchronization

["Damjan Lampret" <lampret@opencores.org>]

Heya,

if you want to invalidate a particular cache line regardless what it
contains, you need to disable cache and then use *CBIR register and write
cache line number in it. This is how for example uClinux invlidates caches
when before it enables them.

regards,
Damjan

----- Original Message -----
From: "Carlos Sanchez de La Lama" <csanchez@teisa.unican.es>
To: <openrisc@opencores.org>
Sent: Friday, January 31, 2003 1:53 PM
Subject: [openrisc] Cache invalidation & synchronization


> Hello!
>
> I wanted to know how could I invalidate a cache line regardless of what it
> contains. As the invalidation register needs to be written with the
effective
> address of contained block to actually invalidate that line, looks like
it's
> not posible to do it.
>
> Best regards!
>
> Carlos Sanchez de La Lama <csanchez@teisa.unican.es>
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