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Re: [openrisc] regression
Hi Damjan,
I used uclinux to compile these two tests from the CVS database (NOT
my own tests) to generate the hex files. I am happy to try your hex files
if you could send them to my email address.
Thank you very much for your quick response.
Michael Phan
----- Original Message -----
From: Damjan Lampret <lampret@o... >
To: openrisc@o...
Date: Thu, 13 Feb 2003 00:04:55 -0100
Subject: [openrisc] regression
>
>
> Michael,
>
> as you can see below it works for me. Can you tell me if you used
> already precompiled hex files or did you build your
> own except test case? I can send you my compiled except test cases
> (hex files) tomorrow if you want to try them.
>
> regards,
> Damjan
>
> $ ../bin/run_rtl_regression single 10
> Wed Feb 12 08:54:02 2003 0.946947 seconds
> Test 1: except-icdc, 40 ms
> Iteration 1:
>
OR1200_REGISTERED_OUTPUTS+FLASH_GENERIC+FLASH_GENERIC_REGIS
TERED+SRAM_GENERIC_REGISTERED
> Iteration 2:
>
OR1200_REGISTERED_OUTPUTS+FLASH_GENERIC+OR1200_CLMODE_1TO2
> Iteration 3: OR1200_REGISTERED_OUTPUTS
>
> <<<
> <<< Iteration 1:
>
OR1200_REGISTERED_OUTPUTS+FLASH_GENERIC+FLASH_GENERIC_REGIS
TERED+SRAM_GENERIC_REGISTERED
> <<<
>
> @@@
> @@@ Compiling sources
> @@@
> @@@ Passed
>
> @@@
> @@@ Building design hierarchy (elaboration)
> @@@
> @@@ Passed
>
> ###
> ### Running test 1: except-icdc, 40 ms
> ###
> ### Passed (@time 6755027.00)
>
> <<<
> <<< Iteration 2:
>
OR1200_REGISTERED_OUTPUTS+FLASH_GENERIC+OR1200_CLMODE_1TO2
> <<<
>
> @@@
> @@@ Compiling sources
> @@@
> @@@ Passed
>
> @@@
> @@@ Building design hierarchy (elaboration)
> @@@
> @@@ Passed
>
> ###
> ### Running test 1: except-icdc, 40 ms
> ###
> ### Passed (@time 4853177.00)
>
> <<<
> <<< Iteration 3: OR1200_REGISTERED_OUTPUTS
> <<<
>
> @@@
> @@@ Compiling sources
> @@@
> @@@ Passed
>
> @@@
> @@@ Building design hierarchy (elaboration)
> @@@
> @@@ Passed
>
> ###
> ### Running test 1: except-icdc, 40 ms
> ###
> ### Passed (@time 17752127.00)
>
> <<<
> <<< End of Regression Iterations
> <<<
> <<< Failed 0 out of 3
> <<<
> $ ../bin/run_rtl_regression single 9
> Wed Feb 12 09:07:23 2003 0.695924 seconds
> Test 1: except-nocache, 60 ms
> Iteration 1:
>
OR1200_REGISTERED_OUTPUTS+FLASH_GENERIC+FLASH_GENERIC_REGIS
TERED+SRAM_GENERIC_REGISTERED
> Iteration 2:
>
OR1200_REGISTERED_OUTPUTS+FLASH_GENERIC+OR1200_CLMODE_1TO2
> Iteration 3: OR1200_REGISTERED_OUTPUTS
>
> <<<
> <<< Iteration 1:
>
OR1200_REGISTERED_OUTPUTS+FLASH_GENERIC+FLASH_GENERIC_REGIS
TERED+SRAM_GENERIC_REGISTERED
> <<<
>
> @@@
> @@@ Compiling sources
> @@@
> @@@ Passed
>
> @@@
> @@@ Building design hierarchy (elaboration)
> @@@
> @@@ Passed
>
> ###
> ### Running test 1: except-nocache, 60 ms
> ###
> ### Passed (@time 9069527.00)
>
> <<<
> <<< Iteration 2:
>
OR1200_REGISTERED_OUTPUTS+FLASH_GENERIC+OR1200_CLMODE_1TO2
> <<<
>
> @@@
> @@@ Compiling sources
> @@@
> @@@ Passed
>
> @@@
> @@@ Building design hierarchy (elaboration)
> @@@
> @@@ Passed
>
> ###
> ### Running test 1: except-nocache, 60 ms
> ###
> ### Passed (@time 4734977.00)
>
> <<<
> <<< Iteration 3: OR1200_REGISTERED_OUTPUTS
> <<<
>
> @@@
> @@@ Compiling sources
> @@@
> @@@ Passed
>
> @@@
> @@@ Building design hierarchy (elaboration)
> @@@
> @@@ Passed
>
> ###
> ### Running test 1: except-nocache, 60 ms
> ###
> ### Passed (@time 36243077.00)
>
> <<<
> <<< End of Regression Iterations
> <<<
> <<< Failed 0 out of 3
> <<<
> $
>
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