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[openrisc] l.trap instruction argument ?

To: <openrisc@opencores.org>
Subject: [openrisc] l.trap instruction argument ?
From: "Scott Furman" <sfurman@rosum.com>
Date: Tue, 11 Feb 2003 12:40:53 -0800
Importance: Normal
Reply-To: openrisc@opencores.org
Sender: owner-openrisc@opencores.org

I noticed an inconsistency between the or1k architecture manual and the
simulator/hardware.  As far as I can tell from reading the code, l.trap
is unconditional in both the simulator and the or1200 implementation.
In the architecture manual, it is described as a trap exception that is
conditionally taken depending on the state of a bit in the SR register.
Which is correct ?

-Scott



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