Re: [openrisc] Bugs detected on or1ksim

["Damjan Lampret" <lampret@opencores.org>]

----- Original Message -----
From: "Scott Furman" <sfurman@rosum.com>
To: <openrisc@opencores.org>
Sent: Wednesday, June 04, 2003 4:06 PM
Subject: Re: [openrisc] Bugs detected on or1ksim


> Carlos Sánchez de La Lama wrote:
>
> >
> >    (2) PICSR bits don't do back to 0 when interrupt line is deasserted.
> >    I think it should, as the Architecture Manual says "Bits in PCSR
> >    represent the status of the interrupt inputs and the actual
> >    interrupt must be cleared in the device, which is the source of the
> >    interrupt".
> >
> >
> FYI, there was once a lengthy discussion on this list centering around
> just that quoted line from the architecture manual:
>
>   http://www.opencores.com/forums/openrisc/2003/02/00049
>
> The outcome wasn't spelled out clearly, but I believe the resolution was
> to remove the offending line from the architecture manual and clarify
> the PIC operation rather than have to change and re-test existing SW.

And the manual was changed at that time. This is what correctly the manual
(in opencores cvs) says about PICSR:

PICSR is used to determine the status of each interrupt input. Bits in PICSR
represent the status of the interrupt inputs and the actual interrupt must
be cleared in the
device, which is the source of the interrupt.

>
> Maybe this goes without saying, but if the patch to or1ksim is applied,
> then a corresponding change has to be applied to the or1200 verilog to
> keep them in sync.

OR1200 RTL is in sync with the above statement about PICSR.

regards,
Damjan

>
> -Scott
>
>
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