Re: Re: [pci] BAR

[Stefan Bergström <stb@viking2001.se>]

Dear friends

To: Miha Dolenc, Isa Servan Uzun
This is not a support forum for PCI builders. Altera and their distributors got (in my experience) very good support organizations. If you are willing to contribute to the development of a free core you are welcome to post it here.
However I can still give you some advice. Buy the 'PCI System Architecture' from MindShare. Pages 49-54 and 70-73 in the 'pci6432 users guide.pdf' has helped me a lot too.

To: Those making the free core
There are lots of cores in the market. Take a look at the documentation of one or more of those and you can get a flying start.
I can only program AHDL myself but if I can help I will be happy. I got some experience now since I have used the Altera PCI core.

Have Fun
STB


-----Ursprungligt meddelande-----
Från:	Isa Servan Uzun [SMTP:uzun@bornova.ege.edu.tr]
Skickat:	den 2 maj 2001 12:44
Till:	pci@opencores.org
Ämne:	Re: [pci] BAR

Hi,

I have a 64-bit PCI Board.
There is 32 I/O lines which are directly connected to the FPGA (Altera
APEX20KE400) on the board.
And there is a 32MB (64-bit * 4M) SDRAM memory on this board.
This board is used to control an external device and acquire data from it.

I need to read and write data (from files on the computer) from/to this
SDRAM. And according to the some control signals (coming from I/O lines)
I need the output a pattern from SDRAM to output I/O lines.

Also I need 3 8-bit Configuration Bytes.
I mean when the user changes this parameter from user interface software on
the host, the I/O
lines should changes according to this chosen value.

For example,

When the user selects number_of_data  (which is one of the 3 configuration
bytes)
is decimal 5 from a pulldown menu, the 8-bit output lines should change to
"00000101" (binary) state.
This value shall indicate to the external device the number of data to be
transferred.

My problem is interfacing with the PCI bus. I have Altera pci_mt64 megacore
function. But as I told you before
I have no experience on PCI.

Thanks for your help.


----- Original Message -----
From: "Miha Dolenc" <mihaPCI@email.si>
To: <pci@opencores.org>
Sent: Wednesday, May 02, 2001 12:04 PM
Subject: Re: [pci] BAR


> Hi,
>
> BAR normally stands for Base Address Register, so if you set it to
> H'FFF00000, then start address of this space is H'FFF00000.
> But I don't know if I understood your question correctly. Value of
> H'FFF00000 looks more like Address Mask to me, which reserves 1MB of
address
> space.
> And a question - isn't address decoding part of PCI core? If it is, there
is
> probably some signal indicating that current access is claimed by your
core.
> If address decoding isn't part of PCI core, than send another email, but
> please describe your problem with more information (all registers that
have
> to be involved in address decoding and their description), so we can help
> you find the right
> solution.
>
> Regards,
>     Miha
>
> ----- Original Message -----
> From: I. Servan Uzun
> To: pci@opencores.org
> Sent: Tuesday, May 01, 2001 1:47 PM
> Subject: [pci] BAR
>
>
> Hi,
>
> I' m learning to use 64-bit pci_core.
>
> I need 1MB of registers. I can reserve 1MByte of system space by setting
> BAR0 to
> "H'FFF00000".
> But this only reserves 1 MB of address space.
> What is the start address of this space and how I can decode it?
>
> Regards,
> Servan
>
>
>
>
>
>

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