[pci] Free PCI core

["Miha Dolenc" <mihapci@email.si>]

Hello, Stefan

nice to hear from you. I'm one of the guys developing free PCI core. What do
we have in mind?
Our core would actually be a fully functional PCI bridge. I don't know, if
you are familiar with WISHBONE SoC bus, to which the bridge would connect.
So, this wouldn't be just an interface core - it would be a functional
bridge with configuration registers already implemented, so only software
would have to be written to start using it. Basic features for the first
version would be:
- 32bit/66MHz
- Delayed/prefetched reads
- posted writes
- 5 programmable address space images for WISHBONE to PCI channel
- 5 programmable address space images for PCI to WISHBONE channel
- Host/Guest bridge implementations

Off course we will need all the help we can get, so we will soon publish a
bit of specs. Then you and others experienced PCI developers will be able to
comment and tell us where we got it wrong or what should be added.
A participation in developement of the core is, off course, highly desirable
by anyone who would like to help. You can participate in developement of the
core if you like - I know AHDL and I can translate it to Verilog(code itself
is not a problem - functionallity is).

Regards,
    Miha