Re: [pci] why read is slower than write ?

[Madhusudhan Rao <madhu_sudhana_rao@yahoo.com>]

hi,
   Thanks for quick response. I am not talking about
open cores. I developed by reading specification.
I am implementing pci target. Let me expalin my doubt
clearly.
When i am reading data from ram(memory) it is taking 3
cycles( 2 are wait cycles), but when i write any data
on same memory it completing in a cycle witout any
wait cycles. I don't have any FIFO's.

Thanks in advance.
Madhu

--- Miha Dolenc <mihad@opencores.org> wrote:
> Hi!
> 
> I don't know what you mean exactly!  Are you talking
> about OpenCores pci
> bridge? Master or Target?
> If you are referring to why PCI Target has 1 initial
> wait cycle for reads
> and none for writes, the reason is because outputs
> must be registered.
> Target has to pull data out of FIFO and put it in
> output registers before
> asserting TRDY.
> Did this help?
> 
> Regards,
> Miha Dolenc
> 
> ----- Original Message -----
> From: "Madhusudhan Rao"
> <madhu_sudhana_rao@yahoo.com>
> To: <pci@opencores.org>
> Sent: Wednesday, March 27, 2002 11:11 AM
> Subject: [pci] why read is slower than write ?
> 
> 
> > Hi,
> >    When i am implementing pci memory read
> transactions
> > i was in a need of keeping 2 wait cycles for
> proper
> > read operation but for write with 1 clock cycle i
> am
> > able to memory write. what may be the reason can
> any
> > body give suggestions. All kinds of inputs are
> > welcome.
> >
> > Thanks in advance
> > Madhu
> >
> >
> > =====
> > MadhusudhanaRao.M
> >
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=====
MadhusudhanaRao.M

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