Re: [oc] Trade off between area and power ?

[Rudolf Usselmann <rudi@asics.ws>]

On Wed, 2003-04-23 at 20:30, NansonHuang@ITRI.ORG.TW wrote:
>  Hi, dear elites,
> 
>   Lately, I am thinking a design problem regarding trade off between area
> and power.
> In the original design, there is 2 copies of complex multiplier(10bits
> inputs/22 bits output) operates at 3.84MHz. If we would like to reduce the
> area, we could just use one copy of it and operates at 2x speed, i.e.
> 7.68MHz. The so called TDM way and just needs some extra control logic to
> dispatch the task. The problem came out. It's a portable system design and
> has limited power could use. How could we determine what kind of
> architecture will we gain on between area and power ? In my opinion, power
> budget should put the first place in portable system. Appreciate for any
> comments.
> 
> All the best,
> 
> Nanson


Theoretically the power consumption of two multipliers
running at 3.84 Mhz should be exactly the same as one
multiplier running at 7.68 Mhz. Assuming the multipliers
are exactly identical.

Power consumption is calculated per gate per Mhz. You
must also take in consideration the toggle rate.

So, lets assume you multiplier has 10K gates, and power
consumption is 0.5 uW per gate per Mhz, and your toggle
rate is 30%.

The multiplier running at 3.84 Mhz would consume 5.76 mW.
The multiplier running at 7.68 Mhz would consume 11.52 mW.

So as you see the two multipliers at half speed consume
the same amount on power as the one multiplier at full
speed.

Of course you have to consider the overhead for the
control logic. Actual number you should be able to
obtain from your ASIC library or the foundry. 

If you want to save even more area you can design a
bit-slice (or digit-slice) multiplier and run it even
higher clock ... depends how far your process will go.

Regards,
rudi
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