Re: [oc] Trade off between area and power ?

[John Sheahan <jrsheahan@optushome.com.au>]

On Wed, Apr 23, 2003 at 09:53:54PM +0700, Rudolf Usselmann wrote:
> So as you see the two multipliers at half speed consume
> the same amount on power as the one multiplier at full
> speed.
> 
> If you want to save even more area you can design a
> bit-slice (or digit-slice) multiplier and run it even
> higher clock ... depends how far your process will go.

this does assume the fast clock can be generated with zero power 
penalty, which is unlikely to be the case.
  
Cever clock gating (the clock, not a CE) is a good way to save
power, but is hard to do well and to analyze. 
john
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