Re: [openrisc] Interrupt servicing

["Robert Cragie" <rcc@jennic.com>]

----- Original Message -----
From: Carlos =?iso-8859-15?q?S=E1nchez=20de=20La=20Lama?=
<csanchez@t... >
To: openrisc@o...
Date: Mon, 23 Dec 2002 18:43:25 +0100
Subject: [openrisc] Interrupt servicing

> I've a question about the Programmable Interrupt Controller. As
> described in
> the Architecture Manual, the interrupt line to the CPU rises
> whenever an
> unmasked interrupt line to the PIC comes up, and it remains on
> active state
> until the actual device drops it. The PICSR is like a mirror of the
> PIC
> interrupt input lines.

That's how I'd expect it to be.

> I'm not really sure, but wouldn't it be better if the interrupt
> could be
> cleared just writting to the PICSR? A very slow device could need a
> long time
> to be accessed, and with current implementation during that time
> there would
> be no way of clearing a interrupt caused by such device. If we
> could write a
> "0" to the correspoding bit in PICSR to make the line go low,
> interrupt
> processing wouldn't be blocked so long. I don't know whether it has
> any wrong
> effects...

If you want to prevent the device interrupting, just mask the interrupt out
in the PICMR. Using clear-on-write would present an ambiguous state of the
associated peripheral.

Robert Cragie, Design Engineer
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Jennic Ltd, Furnival Street, Sheffield, S1 4QT,  UK
http://www.jennic.com  Tel: +44 (0) 114 281 2655
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