Re: [openrisc] List of False Timing Paths for OR1200

["Damjan Lampret" <lampret@opencores.org>]

Hi Ken,

we don't have such a list at the moment. But I can tell you that paths
between dwb_ and iwb_ ports (outside of the or1200 core, in the SoC for
example instantiating the or1200) would be false paths.

regards,
Damjan

----- Original Message -----
From: <kbuttle@nimbuswireless.com>
To: <openrisc@opencores.org>
Sent: Tuesday, February 11, 2003 2:38 AM
Subject: [openrisc] List of False Timing Paths for OR1200


> Dear openrisc engineer;
>
> Do you have a list of false timing paths for the or1200 RISC core, so
> that timing driven layout could be based on an accurate representation
> of circuit performance?
>
> Thank you,
> Ken Buttle
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